Implementation of a QR Decomposition Processor using Walke Mapping on FPGA

Federico D. Camarda,Octavio Alpago,Nicolas Alvarez,Federico G. Zacchigna,Ariel Lutenberg

Implementation of a QR Decomposition Processor using Walke Mapping on FPGA

2016

Federico D. Camarda
Octavio Alpago
Nicolas Alvarez
Federico G. Zacchigna
Ariel Lutenberg

This work presents the development and FPGA implementation of a QR Decomposition Processor capable of solving the Recursive Least Squares (RLS) algorithm.

Keywords:

Matrix decomposition
Recursive least squares filter
Field-programmable gate array
Parallel computing
Algorithm design
QR decomposition
Theoretical computer science
Computer science
signal processing algorithms

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