Optimized placement and routing algorithm for ISCAS-85 circuit

As the characteristic dimension shrinks to the nanometer scale, Multiplication unit in modern processors will become increasingly vulnerable in consuming much power and area. Existing logical optimization for placement and routing approaches in multiplication unit primarily focus on reducing the overhead and power consumption of FPGA's. However, our analysis shows that, the proposed method plays an important role and should be taken into consideration in optimizing the time taken for placement and routing process than the conventional approach. In this work, the proposed a Graph-based analysis algorithm efficiently and accurately reduce area overhead and power consumption of FPGA's. Based on such a model, we propose a novel reliability-oriented logical optimization for placement and routing resources which helps to enhance system-level robustness against area overhead and power consumption. The proposed techniques will be implemented and validated in high end Virtex-6 low power FPGA's of 45nm technology. Experimental results show that, the proposed approach outperforms existing approach in terms of area and power, compared with the baseline versatile place and route technique, the proposed scheme can reduce the area overhead by 20.73%, and decrease the power consumption by 39.44%. The proposed method is analyzed in ISCAS-85-Circuit6288 gives promising option for less overhead and low power application for designing Multiplication unit high end Processors.