VLSI implementation of an eight-state clustering based sequence equalizer

This paper presents the VLSI implementation of a fixed, 8-state CBSE (clustering based sequence equalizer). Simulation results demonstrate superior performance compared to other types of equalizers, such as LTE, DFE and RBF. Furthermore, the architecture presented, does not exhibit performance degradations due to finite wordlength effects. The design was implemented on FPGA using approximately 24000 gates and it can accommodate transmission rates of up to 8 Mbps.