Experimental results of reconfigurable non-binary cyclic ADC

This paper presents a reconfigurable non-binary cyclic analog-to-digital converter (ADC) which can achieve different resolution at different sampling frequency with the same analog conversion stage. The conversion resolution (bit number) of ADC can be increased with more conversion steps in the conventional cyclic manner; and the conversion speed of the cyclic ADC can be enhanced by our proposed multi-rate clock operation mode. The prototype ADC has been designed and fabricated in TSMC 90nm CMOS technology. The measured results of the proposed experimental ADC demonstrate that ENOB=12.42bit is achieved in conventional cyclic ADC mode while Fs=470kHz, and ENOB=9.96bit is achieved in our proposed multi-rate clock mode while Fs=889kHz with the same analog conversion stage and the simple radix-value estimation technique.