Performance improvement of disk array subsystems having shared cache and control memories

Amid trends toward the unification of storage in information systems and improvements in their operating efficiency, increased speed and greater numbers of channels for host connections are needed in disk arrays. In this paper, the authors focus on the fact that for increasing speed the network structure is more useful than the bus structure in terms of an approach for several microprocessors which comprise a disk array and the memory connections shared with them. The authors then propose a hybrid star network configuration which uses a hierarchical star network with connections over switches to cache memory where data from the host is stored temporarily, and a star network with direct connections with control memory where control tables for cache memory and other types of control information are stored. The authors create a disk array with a 32-channel host interface using their approach, and then implement a performance evaluation. The results show that sequential performance of 920 MB per second and transaction performance of 160 kIO per second are achieved. This is equivalent to a 5-fold increase for the former and a 2.5-fold increase for the latter compared to a disk array using a conventional bus setup. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 87(10): 1–14, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20103