A medium-grained reconfigurable architecture targeting high-level synthesis implementation

High-level synthesis is increasingly being used to automatically translate existing software algorithms into hardware quickly and efficiently. Typically, the circuits created by HLS are implemented on Field-Programmable Gate Arrays (FPGAs). While the fine-grained architecture of an FPGA is well suited for general circuit implementation, it can result in excessive routing resource utilization for larger dataflow circuits such as those generated by HLS. As an alternative, we present a medium-grained reconfigurable architecture tailored to implementing HLS generated circuits. The proposed architecture achieves a 5.4x reduction in critical path delay compared to a standard FPGA during initial testing.