Floorplanning with Multi-Phase Clock assignment based on Force Directed Method

Module placement is an important phase for VLSI layout design. Conventional methods for packing problem minimize area and wire-length mainly. Additionally we assign automatically Multi-Phase Clocks each circuit modules to increase processing speed. An effective clock assignment for Multi-Phase Clock VLSI is made by evaluating signal flows. This paper proposes a block packing method using Force Directed Model(FDM) with Hierarchical Clustering(HC). The method assembles modules having strong connection on a cluster. By assigning different clock to each module in a cluster, processing speed of every cluster becomes faster.