The Influence of Gate Bias on the Anneal of Hot-Carrier Degradation

We observe that non-zero gate bias applied during a high temperature anneal following hot-carrier degradation (HCD) impacts degradation recovery in nFETs. The devices are arranged into custom-built arrays and fabricated in a commercial 40 nm bulk CMOS technology and the FET anneal is induced by on-chip poly-Si heaters. The anneal is modeled using Stesmans’ passivation model for P b -defects in hydrogen gas (H 2 ). Negative gate bias improves the anneal, in line with studies on biased passivation of process-induced P b -defects.