Analysis of Feedforward Radix-2^2 FFT 4-Parallel Architecture

A novel approach has been presented to extend radix-feed forward architectures used for the FFT. The future architectures utilize idleness in computation of FFT observations to decrease the hardware intricacy. Different algorithms have been urbanized to decrease the computational intricacy. A novel method to design such architectures from underlying FFT flow graphs. This work presents radix-feed forward architectures which necessitate smaller number of hardware resources than parallel feedback ones. To convert the DFG, we necessitate a downfall set, which is being intended set of actions implemented by the similar functional part.