Parallel Implementation of H.265 Intra-Frame Coding Based on FPGA Heterogeneous Platform

The new video coding algorithm H.265 achieved twice compression rate than the prevailing H.264, but the encoding speed is reduced several times, making it difficult for the real-time applications such as video surveillance and remote meeting. In this paper, we design a parallel intra-frame mode decision architecture based on FPGA to accelerate the coding. We prove that the mode decision problem of multi-level large coding unit of H.265 can be transformed into the accumulation of multiple single-level small coding unit mode decision. Furthermore, we design how mode decision is accelerated by fine-grained parallelism within coding unit, and pipelining among coding units, then implement them on FPGA. The experimental results show that the proposed architecture achieves maximum $93.6\times $ acceleration compare with the ARM A53 platform, with an insignificant loss of video quality.