Implementation of Chaotic System using FPGA

Chaos is one of the major subjects in non-linear science and has been widely studied extensively since the discovery of the Lorenz system. The Chua circuit is a nonlinear circuit characterized by its simplicity and chaotic behavior. It involves a non-linear term initially described by a piece-wise-linear function and displays very rich and common bifurcation and chaos phenomena such as double scroll and multi-scroll. In this article, we use the Xilinx System Generator (XSG) software to simulate the Chua circuit for generating double-scroll and multi-scroll. Design models are produced with 32-bit fixed-point data formats with a fraction of 16 bits, with a clock step size of 0.01 (dt) and implemented on an FPGA to evaluate design performance, including maximum operating clock frequency, resource utilization, and power consumption. This architecture is implemented on the FPGA device Artix7 xc7a100t-1csg324. The results of the hardware co-simulation of the FPGA show the expected outputs of the chaotic generator by Chua.