Patterning solutions for NTD contact hole levels in advanced DRAM nodes

Advanced DRAM technology relies heavily on 193nm immersion lithography. Negative tone develop (NTD) layers are becoming increasingly important particularly in nodes below 20nm. NTD is particularly useful for patterning holes on the wafer. Cut layers for multi-patterning (MP) applications and bit line contact structures are common uses of NTD in DRAM. Patterning these structures pose lithographic challenges around process window (PW), layer to layer overlay, and critical dimension (CD) control. The mask plays a critical role in optimizing all of these attributes. In this paper, we explore multiple mask enhancements to optimize wafer performance for NTD contacts. These include mask process and mask blank conditions, as well as a data enhancement technique generally known as mask process correction (MPC). Specifically, we implement a litho-aware MPC Application (LAMA) for mask pattern fidelity optimization. Finally, we harmonize these mask enhancements with optimizations to wafer exposure conditions and optical proximity correction (OPC) to demonstrate capability improvement in NTD contact lithography.