A900MHz-2GHz low-swing low-power 0.18/spl mu/m CMOS PLL

A fully integrated differential charge-pump phase-locked loop (PLL) is described. The PLL is designed, simulated, and laid out in a 0.18 mum CMOS technology. The PLL lock range is form 900 MHz to 2 GHz. All of the PLL internal signals are differential and low swing (1 V peak-to-peak differential voltage swing). To further reduce the power consumption of the PLL, the charge pump current of 15 muA is used. The PLL operates from a 1.8 V supply while consuming less than 10.5 mW. The complete PLL including its on-chip loop filter occupies 100times190mum 2