Improved Error Correction Capability using Parity Matrix Code

Multiple cell upsets (MCUs) are formed into a serious reliability problem in memory applications. To make fault-tolerant memory cells, Error correction codes (ECCs) are widely used against soft errors for years. In this paper, Parity matrix code is discussed to improve the error correction capability with reduced number of check bits. Maximum error correction can be achieved by parity algorithm. Parity Matrix Code is compared with the existing Decimal Matrix Code in terms of Power and Delay requirements.