Enhanced S/sup 2/I switched-current cells
1996
Enhancements to the basic S/sup 2/I memory cell are presented. These include techniques for compensating the output switches, neutralisation of the feedback capacitances and for improved settling behaviour. The techniques carry minimal penalty for design trade-offs and have enabled design automation of high performance circuits up to video frequencies, using a standard 3.3 V CMOS process.
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