ASIC implementation of a programmable error-trapping decoder for binary codes of length 15

Abstract A pair of encoder/decoder chips has been designed and fabricated based on a gate array implementation. The design of the decoder, the more complex chip, is discussed in the paper. The 10 MHz (max.) decoder, based on a Texas Instruments TAHC10 CMOS gate array, is programmable to detect and correct either random or burst errors for either (15,7) or (15,5) primitive BCH codes. The design employs error trapping techniques, which are described. Hardware and software simulation and the use of ECAD software are reported.