The great interconnect buffering debate: are you a chicken or an ostrich?

One of the often-overlooked aspects of Moore's law is that it is predicated solely on device performance scaling linearly with dimension. Yet scaled interconnect performance has remained essentially constant. The physics of the problem is rather brutal; while capacitance drops with the reduced length of interconnect, its resistance rises and the RC time product is constant under uniform scaling, greatly lagging scaled device performance. In the late-eighties, one micron process dimensions had little wire resistance and the RC delay component of interconnect was negligible. But as process dimensions scaled below one-quarter micron in the late nineties, fears of interconnect delay dominance reached a fevered pitch in the physical design community. Speculation ran rampant that resistive interconnects would soon dominate the performance of design. We dub this era the Rise of the Interconnect Chicken Little.In 1998, Keutzer and Sylvester sought to dispel the hype associated with these wire-related problems, arguing that appropriate device sizing and use of design hierarchy would prevent significant exposure to RC delay in synthesis blocks of 50K gates or less. Their argument was supported by the then-prevalent wisdom that interconnect delay was not dominant and that sharp designers and process engineers could work their way around this problem. We'll dub this general consensus as the Interconnect Ostrich point of view. The following year, Ho and Horowitz attempted to reinvigorate the Chicken Little argument in a publication challenging the Keutzer/Sylvester viewpoint with yet more data on interconnect scaling, but this interconnect-debate-through-papers yielded little change-of-heart on either side. Many other deep-submicron issues have since captured the attention of the designer (e.g., coupling noise, IR drop, and MOSFET leakage) and the interconnect paper-debate generally faded to the background.Recently, however, projections of historical scaling trends by Saxena, et al, have predicted synthesis blocks with 70% (!) of their cell count dedicated to interconnect buffers within a few process generations, raising both skepticism and fearful reactions in the physical design community. While we might think of this as the Return of Chicken Little, the debate has grown far more complex: competition over wiring resources with power supply and clock, concern over noise, and the potential for degraded device performance due to leakage all cast their shadow over this issue. Some now argue we need to consider more exotic circuitry or even restrict our VLSI architectures dramatically. Rather than wait for this debate to rage on in future physical design publications, the time is now to have the Great Interconnect Debate, the subject of this panel.