Low-Voltage Squarer–Divider Circuit Using Level Shifted Flipped Voltage Follower

In this paper, a low-voltage one-quadrant squarer–divider (SD) circuit based on level shifted flipped voltage follower (LSFVF) has been proposed. The proposed squarer–divider circuit utilizes low-voltage SD based on MOS translinear (MTL) principle. In the proposed design, flipped voltage follower (FVF) configuration used for biasing of MTL transistors has been replaced by LSFVF configuration. This proposed LSFVF-based squarer–divider circuit not only maintains the low supply voltage requirement of the FVF-based squarer–divider but it reduces the error present in output current significantly. To validate the working of proposed SD circuit, it has been simulated in LTspice using 0.18 µm CMOS technology. These simulations show that result shows, that a significant improvement is achieved at low values of input current in the proposed LSFVF SD circuit as compared to FVF-based SD circuit.