Design and power optimization of high-speed pipeline ADC for wideband CDMA applications

This paper presents a 7-bit 64 MS/s pipeline A/D converter suitable for wideband CDMA applications. Targeting at achieving low power dissipation at high speed, techniques such as digital correction and optimal scaling of capacitor value have been employed. Switched-Opamp technique is used to further reduce power consumption. This ADC is implemented in 0.5 μm standard CMOS process. It operates from a single 3 V supply, and dissipates only 31 mW at 64 MS/s.