TD-SCDMA/HSDPA Transceiver and Analog Baseband Chipset in 0.18- $\mu\hbox{m}$ CMOS Process

A dual-band time-division synchronous code-division multiple access chipset supporting 2.8-Mb/s high-speed downlink packet access has been demonstrated in 0.18-μm CMOS technology. The receiver adjacent channel selectivity requirement for the transceiver is relaxed by utilizing a high-dynamic-range analog-to-digital converter that allows selectivity improvement in analog baseband and digital baseband. The RX chain achieves 2.8-dB noise figure, -9.4-dBm total third-order input-referred intercepted point, and 5.7% error vector magnitude (EVM). TX delivers 5.0-dBm power, 88-dB gain control, and 4.5% EVM. The TX digital communication system band noise floor is 3 dB below the standard without using a surface acoustic wave filter. Both RX and TX from-idle-to-on switching times are less than 4 μS. Two chips consume 274 and 164 mW on transmitting and receiving, respectively, under a 1.8-V power supply.