Copper Direct Bonding Characterization and its Interests for 3D Integration Circuits

To allow high speed communication between the different strata of a three dimensional (3-D) device, one as to implement a hybridation technique with a very low pitch [1,2]. Patterned metal bonding for 3D-IC is then a key step. Anyway, up to now, thermocompression, eutectic formation, polymer assisted metal bonding or surface preparation in ultra-vacuum and plasma activation were the bonding techniques mainly investigated to enable communication between the different strata of the microsystem [3, 4, 5, 6]. In this present paper, we have investigated the feasibility of a direct hydrophilic coppercopper bonding at room temperature and atmospheric pressure without applying an external stress. This approach has also the advantage to be compatible with microelectronics technologies. N-type (100) 200mm Si wafers were used for this work. A first set of wafers was dedicated for blanket wafer to wafer bonding. They were covered by 500 nm of thermal silicon oxide, 10 nm of TiN and 500 nm of Cu (PVD+ECD). TiN has been used as a copper diffusion barrier. After surface preparation, a 0.4 nm Root Mean Square (RMS) roughness and a 22° hydrophily was achieved. Wafers were then put into contact face to face at room temperature and atmospheric pressure. Bonding was manually initiated. However, the bonding wave speed couldn’t be observed because infra red wavelengths don’t propagate through the copper. Annealing in the [RT400°C] temperature range was used to strengthen the bonding. Scanning Acoustic Microscopy (SAM) was used to evaluate bonding interface quality with respect to annealing temperature. Only few non bonded zones at the edge of the wafers are visible. Bonding energy measurement was performed using Maszara’s razor blade technique [7] as a mode I fracture model, meaning that the contribution of copper ductility on the bond toughness is minimized [8]. The evolution of the bonding toughness: G, and the interface failure location (% sample) was reviewed with respect to the post bonding annealing temperature. The RT bonding energy is almost the theoretical one of the copper/copper bonding (~ 3 J/m) since the surface energy of Cu at room temperature is ~ 1.8 J/m [8]. At room temperature, the bonding interface is straight as observed by Transmission Electron Microscopy (TEM). No void is present at the interface (fig 1). After a 100 °C annealing step for 30mn, copper interdiffusion and grain growth increase the bonding energy up to 3.2 J/m. Since the fracture always starts at the Cu/Cu interface at the edge of the sample, TiN/SiO2 interface is reached only if the Cu/Cu interface toughness is high enough to allow the propagation of the fracture through the copper material. That is why, above 200 °C, the interface failure is mostly located at TiN/SiO2 interface. The 1.4 J/m measured adhesion energy values in these cases are then related to TiN/SiO2 interface. Grain growth, copper interdiffusion and void free interface were observed by TEM analyses (Fig 2). A rough electrical conductivity test has been performed. It reveals an ohmic behavior of the bonding interface when the current is forced to pass through. In order to have first data on the ability of Cu/Cu bonding for multi strata stacking and thinning, a stack of four layers was obtained using this copper bonding process. One of the layers could be grinded down to 7μm highlighting a high bonding energy (Fig 3). No visible defects were observed after 300°C annealing. Moreover direct wafer bonding of Cu/SiO2 patterned surfaces was also performed. Test patterns consisted in Cu 2μm square mesa periodically spaced by SiO2 3μm wide walls. After a 150 °C annealing step, SEM observation highlights the attractive potential of this technology (Fig 4). XRD, SIMS, XRR and other analysis techniques are presently under progress and will be reviewed and discussed.