Memory system and method for strobing data, command and address signals

The memory system is connected to the command, address or write data signals from the memory controller to the memory device, and connect the read data signals to the memory controller from the memory device. Each of the strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data is latched by the quadrature strobe signal coupled from the memory controller to the memory device to the input latch in the memory device. In substantially the same manner, it reads data signals are, using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit is connected from the memory device to the memory controller. A memory system, a memory controller, a strobe signal, command, address, data, input latches, output latches