VLSI Implementation of TDC Architectures Used in PET Imaging Systems

Positron emission tomography (PET) is a medical imaging method based on the measurement of concentrations of positron-emitting radionuclides in a living body. In the PET imaging system, glucose is labeled with a positron-emitting radionuclide and injected intravenously. Then, the positrons move through the tissue and collide with the electrons of the cells in which they interact. As a result of this interaction, two gamma rays are emitted in the opposite direction. Gama rays emitted from cancerous tissue that has retained radioactive glucose are detected through ring-shaped detectors. And the detected signals are converted into an electrical response. Subsequently, these responses are sampled with electronic circuits and recorded as histogram matrix to generate the image set. The gamma rays may not reach the detectors located in the opposite position in equal time. In PETs having TOF characteristics, it is aimed to obtain better positioning information by a method based on the principle of measuring the difference between the reach time of the two photons to detectors. The measurement of the flight time is carried out with TDC structures. The measurement of this time difference at the ps level is directly related to the spatial resolution of the PET system. In this study, 45 nm CMOS VLSI simulations of TDC structures that have various architectural approaches were performed for use in PET systems. With the designed TDC architectures, two gamma photons time reach to detectors have been simulated and the time difference has been successfully digitized. In addition, various performance metrics such as input and output voltages, time resolutions, measurement ranges, and power analysis of TDC architectures have been determined. Proposed Vernier oscillator-based TDC architecture has been reached 25 ps time resolution with a low power consumption of 1.62681 mW at 1V supply voltage.