$\text{SiO}_{2}/\text{SiO}_{2}$ Bonding Technology Research on Wafer-level 3D Stacking

With Moore's Law moving to the limit and the wave of miniaturization, intelligence and multi-functional development of electronic products is launched, expanding the packaging dimension of chips from two-dimensional to three-dimensional is recognized by the microelectronics industry as an effective way to shorten the interconnection length and an ideal solution to improve the chip's functional density. As wafer-level permanent bonding is the key process, this paper studies the ${\text{SiO}_{2}/\text{SiO}_{2}}$ bonding technology based on 12inch wafer. First, the preparation process of BSI-CIS sample is introduced. Then, the low-temperature ${\text{SiO}_{2}/\text{SiO}_{2}}$ bonding mechanism is analyzed, and the bonding process is optimized and determined. The experimental results show that activation time A, annealing temperature B, bonding time C, and bonding force D is the optimal bonding condition based on the 12inch wafer. Finally, the bonding layer is only ${\text{SiO}_{2}}$ , which is a relatively stable inorganic medium and can provide bond strength more than ${2\ \mathrm{J}/\mathrm{m}^{2}}$ . The bond strength has reached to the industry-recognized requirement for wafer level bonding.