A new approach for modeling parametric faults in linear analog VLSI circuits

This paper presents a new approach for modeling parametric faults in linear analog circuits using the concept of ‘backtracking’ through linear analog circuits and statistical analysis using frequency distribution table considering the single parametric faults only. The proposed approach consists of two parts, namely, finding the values of the faulty component at different sampling instants, followed by judicious selection of the faulty component value. The parametric faults are modeled in terms of component tolerance, and determined by simulation and reverse simulation of signal flow graph (SFG) and inverted SFG (ISFG) of linear analog circuits respectively, given the circuit output tolerance, specified by the user. We have also shown that parametric faults are sensitive to the relative change in the nominal values of other fault-free components and frequency of the input sinusoid. The fault modeling approach presented in this paper is analogous to the existing digital test generation method. The effectiveness of the proposed method is verified by fault modeling of a real integrator circuit.