A Compact, Low Jitter, CMOS 65 nm 4.8–6 GHz Phase-Locked Loop for Applications in HEP Experiments Front-End Electronics

This paper presents a compact low-jitter phase-locked loop (PLL) for high-frequency clock generation to be integrated in the front-end electronic readout of high energy physics experiments. The PLL is based on a LC voltage-controlled oscillator with a tuning range between 4.8 and 6 GHz. The PLL features a jitter below 4-ps rms with a power consumption of 18 mW. It has been designed in a CMOS 65-nm technology and occupies a silicon area of just 0.124 mm 2 . Irradiation tests showed that the design is still fully functional after a total dose of 2.5 MGy, with a moderate jitter increase.