Stacked capacitor DRAM process using photo-CVD Ta/sub 2/O/sub 5/ film

Stacked-capacitor DRAM (dynamic random-access memory) cells were fabricated using a high dielectric insulator, tantalum pentoxide (Ta/sub 2/O/sub 5/), which was formed at lower temperature by photo-CVD (chemical vapor deposition) and subsequent photo-oxygen annealing, obtaining a film with low-leakage current and step coverage good enough for a 3-D DRAM cell of more than 16-Mb class. Capitalizing on these features, a novel process for a stacked-capacitor (WSi/sub 2//Ta/sub 2/O/sub 5//WSi/sub 2/) DRAM was developed. In this process, the capacitor is fabricated after the transistor. Since the maximum temperature needed in the capacitor fabrication is 300 degrees C, and is lower than that of the conventional process after contact formation (440 degrees C), the characteristics of the transistor under the capacitor is not affected in this process. This process is compatible with the conventional one, and higher integration is realized without major layout change. >