A selective error data capture method using on-chip DRAM for silicon debug of multi-core design

In multi-core designs, the time overhead for the post-silicon debug is a main challenge because of a large number of cores under debug and the limited resource of design for debug. To overcome this challenge, we propose a selective error data capture method using on-chip DRAM. The key idea is that it is not necessary to capture error-free data of each core. First, the error interval matrix is generated to detect the erroneous intervals of each core by using a multiple-input signature register. And then, the erroneous data capture sequence is used to minimize the number of debug sessions using the debug scheduling algorithm. The experimental results show significant debug time reduction with a negligible hardware overhead compared to the previous work.