A Novel Power Efficient XOR Gate Based on Single Inverted Input

In this paper a novel area optimized XOR gate is proposed. The proposed design is based on the concept of single inverted inputs. The function is also implemented using CMOS and PTL logic. The comparison between the logics is made using power and delay. The novel design using only one inverted input is found to be 80.67% optimized for power in comparison to CMOS logic and 59.59% power optimized in comparison with PTL logic. The tool for implementation is ngspice on 16 nm technology.