IMPLEMENTATION OF SWITCHING CONTROLLER FOR THE INTERNET ROUTER

The greedy scheduling (GS) algorithm is a scalable maximal matching algorithm. This algorithm was conceptually proposed and well received since it provides non-blocking in an Internet router with input buffers and a cross-bar, unlike other existing implementations. In this paper, I implent a new design of the GS algorithm, and determine its exact behaviour, performance and QoS that it provides. I design and measure the performance of their implementations in terms of their scalability and speed. It will be shown that multiple scheduler modules of a terabit Internet router can be implemented on a low-cost fieldprogrammable gate-array (FPGA) device, and that the processing can be performed within the desired time slot duration. The scheduler modules designed on one low-cost Altera FPGA may control router with hundreds of ports. The output selection time remains below 60 ns in high-capacity Internet routers.