Hot Spot Dynamics in Quasi Vertical DMOS under ESD Stress

Quasi vertical DMOS transistors in a 90V Smart Power Technology are studied under ElectroStatic Discharge (ESD) stress. Movement of current filaments and multiple hot spots are observed ouder snap-back conditions. The hot spot dynamics are explained in terms of the movement of a base push-out region across the cell field as a consequence of the temperature dependence of avalanche generation. The described mechanisms help homogenizing the time averaged current density distribution and enhance the device robustness against ESD events.