Printability verification for double-patterning technology

For keeping pace with Moore's Law of reducing the feature sizes on integrated circuits, the driving forces have been reductions in the exposure-tool wavelength, and increases in the lens numerical aperture (NA). With extreme ultra-violet (EUV) lithography and 3rd-generation immersion delayed for production use, these driving forces are now stalled at a wavelength of 193 nm and an NA of 1.35. Therefore, double-patterning technology (DPT) is needed for printing 22 nm device node features. With DPT, a 22 nm layout is split into two patterns. Each pattern is printed using 32 nm node lithography technology, and the original pattern is recovered by a logical summation (the Boolean OR operation) of these two separately exposed patterns. DPT presents several challenges for printability verification. First, the etch target can be very different from the resist target because significant biasing is used to improve the lithography process window. Second, overlaps between the two patterns produce new problems such as sharp-cornered pinching at pattern junctions, and bridging between patterns. Finally, there are additional process variations: misalignment between the two patterns, and twice as many dose and defocus dimensions. We present results from a full-chip DPT-verification tool that addresses these challenges. We also provide examples of lithography problems that are specific to DPT, and describe possible guidance for the resolution enhancement techniques (RET) and design tools.