Design Optimization Techniques of a Phase Interpolator for High-Speed Applications

This paper presents the design optimization technique for a phase interpolator(PI) and suggests the inductor-loaded PI structure for low power consumption suitable for high-speed applications. An analytical study leads to the design criterion composed of the process constants for the minimum power consumption and the proposed inductor-loaded PI reduces the power by half with determined bandwidth and gain of PI. Designed 7-bit PI using 1.2V CMOS technology consumes in 12GHz with inductor and the suggested optimization technique.