Modeling in the Cloud: Web Hosted CPI Modeling for Fabless Design Houses and OSATs Method for Mechanical Stress Simulation across the Chip & Package Domains in 3D IC's

Chip-Package Interaction (CPI) is a significant concern for modern electronic devices and this concern is magnified for 3D Stacked IC. Hard bumps, soft dielectrics, thin die and complex geometries of the stacked die require ability to model and evaluate the interactions and risks. In packaged IC, dissimilar materials along with the thermal history during the assembly process results in significant residual stresses. These stresses can impact process yields, reliability and die electrical performance. Traditionally modeling and evaluation of these risks have been handled by different groups/companies (foundry, OSAT, Fabless Device Mfg) and have been hindered by the difficulty of using different tools and more importantly collaborating without revealing proprietary models and process information/recipes. In this paper we present a modeling flow which incorporates an interface between the tools traditionally used for both package and silicon modeling. This is accomplished by utilizing Boundary Conditions (BC...