Silicon epitaxy process recipe and tool configuration optimization

Silicon epitaxy is widely used in semiconductor fabrication due to its ability to produce high quality and low cost thin film. Epitaxy optimized process condition with respect to the process recipe and tool for the maximization of n-type epitaxial production has been investigated. For standard recipe of an epitaxy process, there are seven main steps, namely purge, ramp, bake, stab, deposition, post and cooling. This project focuses on the recipe optimization on ramp, bake and stab steps. For the tool configuration, cool-down step has been optimized. Impact on slip, haze, wafers warpage and crystal originated particles have been investigated.