A new register file structure for the high-speed microprocessor

The pipeline operations of the register file in a microprocessor are analyzed in detail. Conventional register files, two-port static RAMs, have two problems in successive write-to-read operations. (1) A read-time error takes place when the transition of the W/R mode and the transition of register address occur simultaneously. (2) A write-time error takes place when the supply voltage is slow. A new register file structure is proposed, which has three address word lines and four data bit lines for each memory cell. This structure enables the independent write and read operations to each other, and can solve the two problems. By using this register file structure, a new 16 bit microprocessor with 250 ns machine cycle time is successfully developed. Several other features of this processor are also explained and discussed.