An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations

Due to aggressive technology scaling in nanometer regime, the impact of process variations on IC design has become a challenge. Process variations are usually classified into two types: inter-die and intra-die variations. The focus of this paper is on intra-die variations, which were ignored in the past, and are now significantly impacting the performance of modern circuits. A novel statistical gate-sizing metric is proposed to enhance the performance of digital integrated circuits in the presence of local intra-die process variations. The metric selects the most beneficial gates to be resized for improving circuit performance at a lower area cost. The proposed gate-sizing metric provides a means to increase yield leading to better chip revenue.