Adiabatic quasi 6T-SRAM with shared writing and reading ports

An adiabatic quasi 6T-SRAM is proposed in which a memory cell shares the writing and reading ports between a flip-flop and a bit line so that the transistor number in a memory cell is decreased to about six. The gradual charging operation in the circuit can avoid electromigration and hot carrier effects. In the writing mode, the voltage of the memory cell power line is reduced to ground gradually by using a high-resistivity nMOSFET, and the nMOSFET is turned off to set the memory cell power line in a high-impedance state. Then, adiabatic signal from the shared writing port is input to charge the memory cell power line to VDD. In the reading mode, the shared reading port, which connects the flip-flop and the bit line, is used for stable operation. The bit line can be precharged to a small value (for example, VDD/4), which enables a small current flow during the reading mode. Logic data are read by sensing the voltage decrease in the precharged bit line.