Integrated transistor arrangement with a plurality of lateral transistors

There is disclosed a transistor arrangement. The transistor device includes a semiconductor layer, a plurality of transistors, each having a load path and a control terminal, and at least two doped load terminal areas, which are arranged in a first lateral direction of the semiconductor layer spaced from each other and each extending in a vertical direction of the semiconductor layer. The load paths of the plurality of transistors are connected in series between a first load terminal and a second load terminal of the transistor arrangement and each of the plurality of transistors is at least partially integrated into the semiconductor layer. A control terminal of the transistor arrangement is connected to the control terminal of a first transistor of the plurality of transistors. The load path of a second transistor of the plurality of transistors extends between the at least two load terminal areas. A first load terminal area of ​​the at least two load terminal areas forming a load terminal of the first transistor and a load terminal of the second transistor. The first load terminal area extending deeper than at least one active device region of the first transistor in the vertical direction of the semiconductor layer.