Plasma etch challenges for porous low-k materials for 32nm and beyond

The challenges facing back-end-of-line (BEOL) etch as technology nodes progress are becoming increasingly difficult as the challenges due to shrinking dimensions are compounded by the challenges from new materials integration. Materials 100nm, new interactions of the materials with this critical dimension need to be considered. Both single and multipatterning schemes are considered, with some of the new challenges due to the multi-patterning schemes being highlighted. The need for a trench-first-via-last patterning scheme will also be reviewed in the context of advanced patterning nodes where M x -to-V x-1 spacing, via chamfering, and metal fill compatibility are key concerns. In addition, for trench double patterning, there is increased focus on the same-color tip-to-tip and tip-to-side rules, requiring etch to focus on CD control capabilities not only for the line CD but also for the line end, and line ends have always been a key challenge for k ≤ 2.55 etching, where metallization is most sensitive to dielectric damage structural effects. This paper will review several different patterning approaches and analyze the etch challenges as a function of dimensions, materials, or a combination of both.