A comparative analysis of some multi-gate junctionless transistors

Absence of p-n junctions and associated electrical drawbacks coupled with the ease of fabrication of multi-gate (MG) architectures have rendered junctionless transistor (JLT) a promising candidate for future very large scale integrated (VLSI) circuits in line with the Moore's law. In this paper, we have presented a comparative analysis on the performance of double gate (DG) and Gate-all-around (GAA) JLTs along with the underlying analytical expressions used for such computations and the same has also been validated. The effect of variation of different device parameters such as oxide thickness, body thickness, doping concentration etc. on some electrical characteristics of DG and GAA MOSFETs have been investigated. We have also explored the impact of variation of aspect ratio and the use of multiple channels on the performance of GAA JLTs.