Deep Depletion Capacitance-Voltage Technique For Spatial Distribution of Traps Across the Substrate in MOS Structures

Abstract It is important to characterize the distribution of spatial traps in the MOS structure for separating the interface states from the subgap density-of-states. In this study, we report a characterization technique for the spatial distribution of traps using the C-V characteristics under deep-depletion bias. Depletion capacitance is determined by the depletion depth (Xd) and the dielectric constant with the MOS structure. Thus, the distribution of spatial depletion charges can be identified if only the depletion capacitance can be separated from the measured gate capacitance. In the case of MOS structure with spatial traps in the element, it will show a deviated characteristic from the ideal depletion capacitance. Therefore, this allows us to characterize the spatial distribution of traps in MOS structures. The spatial distribution of traps from a single crystal silicon MOS capacitor was extracted Ntrap,max=3.45 × 1018 cm−3 ass the maximum value in the interface, indicating that the concentration tends to decrease more in the substrate direction.