Photolithography study for advanced packaging technologies
2016
In recent years, demand for high density integration of semiconductor chips has steadily increased due to miniaturization and high-performance requirements of electronics including Smartphones and Tablet PCs. In addition to 3D integration using Through Silicon Via (TSV) technology and 2.5D integration technology using silicon interposers, Fan-Out Wafer Level Packaging (FOWLP) using redistribution processes over chip size has become a hot topic these days.
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