An automated tool for chip-scale ESD network exploration and verification

This paper describes a tool for full-chip static ESD (ElectroStatic Discharge) verification called ESD IP Explorer. The tool feasibility is first demonstrated on a 64-pin custom R&D testchip. Its scalability is tested in a second example involving a 138mm² 3,066-bump prototype, which basic verification is performed in less than 8 hours. Both examples are in 28nm UTBB (Ultra-thin-body and BOX — Buried Oxide) FD-SOI High-K metal gate technology. More advanced static verification features are finally discussed.