Multi-processor based CRC computation scheme for high-speed wireless LAN design

Presented is a software cyclic redundancy check (CRC) parallel computation scheme for the realisation of a high-speed wireless communication system on a multi-processor design platform. The proposed CRC generation scheme was applied to the IEEE 802.11n WLAN system. As a result, the proposed CRC scheme is capable of meeting tight latency constraint to achieve 144 Mbit/s throughput at a processor frequency less than 200 MHz, when evaluated with register-transfer-level simulation.