Physical co-design for micro-fluidically cooled 3D ICs

The excessive heat accompanying high performance 3D ICs requires the use of aggressive cooling solutions such as interlayer micro-channels. However, interlayer micro-fluidic cooling comes with overheads such as conflict with through silicon vias (TSVs). Conventional approach which incorporates cooling after the design of the 3D system ([20]) could suffer significant overheads (e.g. substantially increasing chip area, wire-length etc.) in order to realize thermally-feasible designs. In this paper, we present a co-design approach to achieve sufficient cooling with compact layout in 3D ICs with micro-channel based fluidic cooling. Our approach follows a hierarchical partitioning based technique to simultaneously place the gates, TSVs as well as interlayer micro-channels. Simulation results illustrate that, by realizing thermally-feasible design, our algorithm achieves an average of 40.2% and 10.94% saving in chip area compared to air cooling and the method of allocating micro-channels after the design of 3D systems, respectively.