Parallelization resources of image processing algorithms and their mapping on a programmable parallel videosignal processor

For the design of a highly parallel programmable video signal processor, the parallelization resources and characteristic properties of image processing algorithms have been analyzed. Basing on the resulting algorithmic requirements, an architecture for a reduced instruction set processor with parallel data paths, called HiPAR-DSP, has been deduced. The processor consists of 4 or 16 parallel data paths with local data caches, coupled by a shared memory with matrix type data access. Control, memory and arithmetic architecture of the processor are properly balanced and adapted to the control flow and data access patterns of algorithms, resulting in a remarkable high sustained processing power for a broad spectrum of image processing algorithms.