A Preliminary Evaluation of Timing-Speculative Instruction Collapsing

The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. We are investigating a typical-case design methodology, which we call the Constructive Timing Violation (CTV). This paper extends the CTV concept to collapse dependent instructions, resulting in performance improvement and power reduction. Based on detailed simulations, we find the proposed mechanism effectively collapses dependent instructions.