Wafer Bonding for Soi

Bonding of 3 and 4 in. oxidized silicon wafers was investigated for SOI applications. The bonding was achieved by using a surface treatment procedure compatible with VLSI processing and by heating in an inert atmosphere a pair of wafers which had been contacted face-to-face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation was developed. The bond strength was found to increase with the bonding temperature from about 60-85 erg/cm2 at room temperature to ⋍2200 erg/cm2 at 1405°C, in good agreement with the surface energy of bulk quartz. The strength was essentially independent of the bond time for up to 1100°C. Electrical properties of the wet-oxide-to-wet-oxide bond were tested using MOS capacitors. The results were consistent with a negative interface charge density of approximately 1011cm−2 at the bond. A double etch-back procedure was used to thin the device wafer to the desired thickness within *20 nm across a 3in. wafer. The density of threading dislocations in the remaining silicon layer was smaller than 103 cm−3, and the residual dopant concentration less than 5×l015cm−3, both remnants of the etchstop layer. A discussion of the bonding mechanism will be presented.