Development status of gate-first FeFET technology

Recent progress on FeFET gate-first technology development is presented. New characterization results from FeFET endurance degradation are shown and assigned to interfacial layer degradation. Two methods to overcome endurance degradation in terms of proper choice of device geometry or program / erase algorithms are highlighted. Moreover, statistical variation of FeFET memory states is characterized for single memory cells as well as mini arrays across wafer. This is complemented by 136 Kbit FeFET array results which demonstrate tail-to-tail separation of ~3μA which represents the basis for read-out operations below 25 ns. Latest results from FeFET variability from 180nm x 180nm as well as 72nm x 72nm memory cells is presented and a 32 Mbit macro incorporating 180nm x 180nm cells has been designed for future characterization.